Method of semiconductor device fabrication

ABSTRACT

A method of semiconductor device fabrication comprising forming at least the indentation in a surface of a semiconductor body. The indentation is partially filled with a filler material such that walls of the indentation are exposed above an upper surface of the filler material. First and second dopants are introduced through the exposed walls of the indentation and first and second doped regions formed. The first doped region extends into the semiconductor body around the filled portion of the indentation to a first region boundary which is at a predetermined first depth relative to the upper surface of the filler material. The second doped region extends into the semiconductor body around the filled portion of the indentation to a second region boundary which is at a predetermined second depth relative to the upper surface of the filler material. The first and second depths are different such that a region of predetermined thickness is defined adjacent the indentation between the first and second boundaries.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a method of semiconductor device fabrication,and particularly but not exclusively to a method for fabricating powertransistors with a vertical channel MOS gate structure.

2. Description of Related Art

Conventional vertical DMOS power transistors are known having aplurality of ‘cells’, each cell comprising a gate disposed on anuppermost surface of a wafer, and a source region located adjacent alower surface of the gate. A body region is provided beneath the gateand adjacent the source, such that in an on-state a field from the gateforms a horizontal conducting channel in the body, allowing current toflow laterally across the body regions, and through a drain regionlocated between and beneath the body regions to a drain contact locatedat a lowermost surface of the substrate. Such conventional DMOSstructures suffer from the presence of a parasitic Junction-FET regionlocated between adjacent cells, the resistance of which increasesrapidly as the spacing between adjacent cells is reduced below acritical dimension. This mechanism creates an inherent packing densitylimitation, restricting the extent to which on-state resistance in theconventional vertical DMOS structure may be reduced by means of geometryscaling.

The above limitations are mitigated by an alternative known UMOSstructure in which the gate regions are disposed adjacent to thevertical sidewalls of U-shaped indentations or trenches formed in awafer surface. An associated source region is disposed adjacent theupper part of each gate, and a body region is located directly below thesource. When the gate region is turned on, a field penetrates from thegate into the body region, thereby forming a vertical conducting channelwhich allows current to flow vertically between the source and thedrain. Because UMOS structures feature such vertical rather than lateralchannel regions, they have no parasitic Junction-FET elements and thusdo not suffer from the limitations that these elements impose on theconventional DMOS structure.

A method of fabricating a UMOS structure with self-aligned sourceregions is known from British Patent Specification No. GB 2 264 388. Inthis known method, a p-type (body) semiconductor region is formed on topof an n-type (drain) semiconductor layer. Practically, the p-type regionis likely to be formed either by means of a doped epitaxial depositionof specified thickness onto the surface of the n-type layer, or by theintroduction of p-type dopant into the surface of the n-type layerfollowed by thermal processing to determine the junction depth. Amaterial (typically silicon-dioxide) is grown or deposited on the topsurface of this structure and is selectively etched to form a trenchmasking layer. Trenches or grooves are then formed beneath the aperturesin this mask such that they extend from the surface through the p-typeregion and part-way into the n-type region. A dielectric layer is thenformed on the walls of the grooves, and the grooves are partially filledwith a gate electrode material, for example polysilicon. This gateelectrode material is either deposited at a layer thickness whichresults in partial filling of the grooves, or (more practically) isinitially deposited such that it fills the grooves completely, and thenetched back to leave the grooves partially-filled. With thetrench-masking layer still in place on the first surface, source dopantis then introduced into the exposed sidewalls of the grooves, above theetched-back gate electrode.

The above known method has advantages with respect to earlier structures(for example that described in FIG. 17 of GB 2 264 388, in which thesource dopant is introduced selectively via the substrate surface)because it is not necessary to define via photolithography and with ahigh degree of accuracy the lateral positional relation between thesource regions and the grooves. This allows the distance separatingadjacent grooves to be reduced and thereby a higher density of groovesimplemented, improving on-state performance. However the methoddescribed with reference to FIG. 16 of GB 2 264 388nevertheless stillexhibits disadvantages in that the vertical distance separating thesource regions from the drain region, known as the channel width, isdependent on the final etched-back position of the top of the gateelectrode material. This position is in turn a function of both theinitial depth of the grooves, the depth of the initially-deposited gateelectrode layer and/or the precise amount of gate electrode materialremoved during the etchback process step. Variations in these parametersintroduce inconsistencies into the channel width dimension, aspractically fabricated using this method. It is desirable to minimisethe channel width dimension in order to optimise performance when thestructure is active, and these inconsistencies restrict the degree towhich this can be practically achieved.

SUMMARY OF THE DISCLOSURE

It is an object of the present invention to obviate or mitigate theabove-described disadvantages.

In accordance with the present invention, there is provided a method ofsemiconductor device fabrication comprising forming at least oneindentation in a surface of a semiconductor body, partially filling theindentation with a filler material such that walls of the indentationare exposed above an upper surface of the filler material, andintroducing and diffusing first and second dopants through the exposedwalls of the indentation to form first and second doped regions, thefirst doped region extending into the semiconductor body around thefilled portion of the indentation to a first region boundary which is ata predetermined first depth relative to the upper surface of the fillermaterial, and the second doped region extending into the semiconductorbody around the filled portion of the indentation to a second regionboundary which is at a predetermined second depth relative to the uppersurface of the filler material, the first and second depths beingdifferent such that a region of predetermined thickness is definedadjacent the indentation between the first and second boundaries.

Preferably, the indentations are elongate trenches, and may haveU-shaped cross-section.

The step of partially filling the indentations with a filler materialmay comprise filling completely the indentations with filler material,then etching the filler material part way into the indentations.

Preferably, the filler material is polysilicon.

Preferably, a layer of dielectric is formed upon surfaces of the trenchprior to the trench being partially filled. Dopant may be introducedinto the side walls of the trench through this dielectric layer.Alternatively, the dielectric layer may be at least partially removedfrom those surfaces of the trench which are exposed above the partiallyfilled portion of the trench, prior to the introduction of dopant.

Preferably, at least a portion of the trench masking layer is retainedon the said surface of the semiconductor body and functions as a barrierto introduction of at least one of the dopants.

Preferably, at least one of the dopants is produced by an ionic sourcewhich is disposed at an angle to the trench.

In one embodiment, the first dopant is arranged to penetrate furtherinto the side walls of the trench than the second dopant, and the seconddopant is prevented from entering at least part of the first surface ofthe semiconductor by means of an at least partially retained trenchmasking layer on the first surface. The thickness and composition of thetrench masking layer may be chosen such that it functions as aneffective barrier to an implant of the second dopant carried out at lowenergy, but is a relatively poor barrier to an implant of the firstdopant carried out at high energy. Preferably in this embodiment, thesemiconductor device is a MOSFET with gate electrode regions provided bythe filler material, and body and source regions provided by the firstand second doped regions.

In an alternative embodiment the choice of dopant species and diffusionconditions is such that the second dopant penetrates further than thefirst, the first dopant providing the MOSFET source region and thesecond dopant the MOSFET body region. In this case, the masking layerused to define the trench etch is at least partially retained at thestage of first (source) dopant introduction, but may be partially orwholly removed prior to introduction of the second (body) dopant,enhancing the degree to which body dopant enters the substrate via thefirst surface.

In any embodiment the MOSFET may be a n-p-n (n-channel type) or a p-n-p(p-channel type) structure.

The semiconductor body may be formed on a further body of semiconductorwhich defines a drain region. A further layer of opposite conductivitytype to the further body of semiconductor may be formed on the side ofthe further body of semiconductor remote from the said surface of thesemiconductor body.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described by way of example,with reference to the accompanying drawings, in which:

FIG. 1 is a schematic illustration of a cross-section of a part of asemiconductor body covered by a mask;

FIG. 2 is a schematic illustration of the cross-section of FIG. 1 aftertrenches have been etched into the semiconductor body;

FIG. 3 is a schematic illustration of the cross-section of FIG. 2 afterthe trenches have been coated with oxide material;

FIG. 4 is a schematic illustration of the cross-section of FIG. 3 afterthe trenches have been partially filled with polysilicon;

FIG. 5 is a schematic illustration of the cross-section of FIG. 4 afterthe semiconductor body has been doped with p-type dopant;

FIG. 6 is a schematic illustration of the cross-section of FIG. 5, afterthe semiconductor body has been doped with n-type dopant; and

FIG. 7 is a schematic illustration of a cross-section of part of an-channel (n p-n) UMOS device which has been fabricated according to theinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1, a semiconductor body is formed on a substratedefining an n+ type semiconductor drain region 1. The semiconductor bodycomprises an n type drain region 2 extending to an upper surface 3 ofthe semiconductor body which supports a masking layer 4 which may beselectively removed by etching to define areas where trenches are to beformed in the region 2. The drain region 2 may be an epitaxial layer.The masking layer 4 may comprise a single material type, for examplesilicon dioxide, or it may be a multi-layer comprising several differentmaterials, for example silicon dioxide/silicon nitride/silicon dioxide.After selective removal of the mask 4, trenches are etched to apredetermined depth through the exposed surface 3 and into region 2, asshown in FIG. 2, using a known method, for example reactive ion etching.

Typically, the illustrated multi-layer structure will be formed on awafer substrate which might he 600 μm thick. The substrate in effectforms the drain region 1 of FIG. 1. The layers 2 and 4 built up on thesubstrate will be very much thinner than the substrate itself. Forexample, the region 2 may be 6 μm thick. The layer 1 is shown in theFigures as being relatively thin simply for the purposes ofillustration.

An insulating layer 5 is formed using a known technique on the walls ofthe trenches as shown in FIG. 3. One such known technique is thermaloxidation. Layer 5 may also be formed as a composite oxide/nitridelayer. Some or all of the layer 5 may comprise deposited material.Following layer 5 formation, a gate material 6, for example polysilicon,is introduced into the trenches, for example using a low pressurechemical vapour deposition technique. The polysilicon gate material 6 isarranged to partially fill the trenches, as shown in FIG. 4, for exampleby first filling the trenches and then etching back some of thepolysilicon 6. The polysilicon 6 may be doped to effect an improvementin conductivity. This may be done during or after deposition. In analternative method, aluminium gates may be arranged partially to fillthe trenches, without requiring to be etched back, using a methoddescribed in WO 9700536.

Referring to FIG. 5, p-type body dopant is introduced laterally intoregion 2 through the sidewalls of the trenches. The body dopantintroduced through the trench sidewalls initially remains close to thosesidewalls. The dopants are then diffused to form p-type body regions 7.The body dopant may be introduced into the trench sidewalls usingcharged dopant ions (for example ionic boron) which pass directlythrough the oxide layer 5 and into the region 2. The ions may bedirected into the trenches using for example an angled source, divergentsource or an isotropic source. More than one implant step may be used tointroduce the total body dopant, for instance a separate source for eachside of the trenches may be utilised. The composition and thickness ofthe trench masking layer 4, and the energy of some or all of the bodyimplants, may be chosen such that some body dopant enters the uppersurface of the substrate through the masking layer 4, as well aslaterally through the trench sidewall. For example, although not shownin FIG. 5, dopant penetration into the upper surface 3 of thesemiconductor may be enhanced by prior partial etching of the maskedlayer 4 in the vertical direction in order to reduce its thickness.Alternatively or in addition, one dopant may be ion implanted at arelatively low energy, such that the mask 4 is not penetratedsubstantially by the dopant, whereas the other dopant may be implantedat a relatively high energy such that the mask 4 is substantiallypenetrated by the dopant. Alternatively, other known methods of dopantintroduction may be used, for example gaseous predeposition. Somemethods may require that the oxide layer 5 is first removed from thewalls of the trenches above the gate material.

The position of the boundary between the body regions and then-substrate region depends upon the distance penetrated by the bodydopant within the substrate, and upon the vertical position of an uppersurface of the gate material 6 within the trenches. The penetrationdistance can be closely controlled, and therefore the position of theboundary relative to the upper surface of each gate region 6 isaccurately determined.

Referring now to FIG. 6, source dopant is introduced laterally throughthe side walls of the trenches, using a technique such as one of thosedescribed above, to form source regions 8. As illustrated, the sourcedopant is implanted through the oxide layer 5 on the trench wall, but itwould be possible to remove the outer layer 5 before the introduction ofthe source dopant. The source dopant is prevented from entering at leastpart of the upper surface of the substrate by those portions of thetrench masking layer 4 which have not been removed. The diffusion of thesource dopant is arranged such that it penetrates to a lesser distancethan the body dopant, so that a portion of body region 7 is interposedbetween each source region 8 and drain region 2. The penetrationdistance of the source dopant is closely controlled such that theposition of the boundary between the regions 7 and 8 relative to theposition of the upper surface of each gate region 6 is accuratelydetermined. It will be appreciated that driving in the source regions 7may cause some further diffusion of the dopant forming the body regions8, but this further diffusion can be taken into account when determiningthe desired relative positions of the source and body region boundaries.

Since any variation in the vertical position of the upper surface ofeach gate region 6 affects the vertical penetration distance of bothbody and source dopants equally, the vertical extent of body region 7between the sources 8 and the drain region 2 will be substantially thesame throughout the lateral area of the substrate. Consequently, thevertical thickness of the portion of body region 7 interposed between asource region 8 and the drain region 2, known as the channel width, isaccurately determined.

The fabrication method is completed, as shown in FIG. 7, by isolatingthe uppermost surface of the etched-back polysilicon gates 6 with aninsulating material 9, and by completely removing the mask 4 to exposethe upper surface of the silicon. A layer of metal 10 is then added tothe upper surface of the structure, to form an electrical contact to thesource and body regions. A shallow p-type implant may additionally becarried out, after the removal of layer 4, in order to boost the p-typedopant concentration and thereby improve the electrical contact betweenthe body regions 7 and the metal region 10. The gate regions 6 will beconnected elsewhere to a gate contact metallisation region.

In any of the above embodiments p and n type regions may be interchangedthroughout to arrive at a p-channel (p-n-p) rather than n-channel(n-p-n) structure.

In any of the above embodiments, an additional layer beneath layer 1 andof opposite type to layer 1 may be present, resulting in the formationof a n-channel or p-channel IGBT structure.

The attached drawings show the formation of two adjacent trenches. Itwill be appreciated that the method of the present invention may beapplied to a wide variety of trench configurations, for example theformation of a hexagonal array in which trenches are etched in spacesdefined between a tightly packed array of hexagonal mesa areas on thesurface of a substrate.

The above-described method refers to an embodiment in which thefirst-introduced dopant forms the body regions 7 and thesecond-introduced dopant forms the source regions 8. An alternativepossibility is that the second-introduced dopant is arranged topenetrate to a final position deeper than the final position of thefirst-introduced dopant. In this case the second-introduced dopant formsthe body regions and the first-introduced dopant forms the sourceregions. This is a feasible approach, at least in the fabrication of ann-channel structure, due to the different rates of diffusion of thedifferent dopant species usable for body and source regions, and thepossibility of using ion implantations at different energies for theintroduction of each dopant. The advantage of such a method is thatremaining portions of the trench mask 4 can be used to mask the first(source) dopant, but removed before the introduction of the second(body) dopant, such that body dopant enters the upper surface of thesemiconductor body as well as the trench sidewalls.

A further possibility is to diffuse (drive-in) both dopantssimultaneously following an initial introduction of both source and bodydopants. This approach has two advantages. Firstly, both body and sourcedopants are subjected to exactly the same drive-in conditions, so thatany unintentional wafer-to-wafer and batch-to-batch variations inmanufacturing conditions, e.g. related to furnace operation, are appliedto both dopants equally, thereby improving uniformity in the finalchannel width. Secondly there is an associated reduction in thecomplexity of the manufacturing process, as separate body and sourcedrives are replaced by a single drive.

As a consequence of any of the above methods of production, the channelwidth of a resulting UMOS structure is dependent only on the diffusiondistances of the body 7 and source 8 regions, since both are aligned tothe same physical feature (i.e. the position of the top of theetched-back gate polysilicon 6). Variations in the position of thisfeature do not alter the relative positions of the body 7 and source 8,and therefore do not alter the vertical extent of the channel widthregion between the source 8 and drain region 2. This allows the verticalextent of the channel to be optimised with greater precision than ispossible with prior art fabrication methods. The junction depths aredetermined by the lateral introduction of the body and source dopantions, which provides for substantially identical and uniform depths ofbody 7 and source 8 at every position within the device active area,thereby ensuring that the critical ‘channel width’ dimension issubstantially uniform across the device active area.

In contrast to other known methods of UMOS fabrication, the presentmethod requires no critical mask alignments. This allows a substantialreduction in lateral dimensions within the active area of the UMOSstructure, and a corresponding increase in the density of UMOS trenchedge per unit area. Regions of p+ doping in the body regions, commonlyseen in the prior art, are unnecessary due to the very close spacing oftrenches, which spacing is made possible by the absence of criticalmasking of the source regions.

What is claimed is:
 1. A method of semiconductor device fabricationcomprising forming at least one indentation in a surface of asemiconductor body, partially filling the indentation with a fillermaterial such that walls of the indentation are exposed above an uppersurface of the filler material, and introducing and diffusing first andsecond dopants through the exposed walls of the indentation to formfirst and second doped regions, the first doped region extending intothe semiconductor body around the filled portion of the indentation to afirst region boundary which is at a predetermined first depth relativeto the upper surface of the filler material, and the second doped regionextending into the semiconductor body around the filled portion of theindentation to a second region boundary which is at a predeterminedsecond depth relative to the upper surface of the filler material, thefirst and second depths being different such that a region ofpredetermined thickness is defined adjacent the indentation between thefirst and second boundaries.
 2. A method according to claim 1, whereinthe indentation is an elongate trench.
 3. A method according to claim 1,wherein the step of partially filling the indentation with a fillermaterial comprises filling completely the indentation with fillermaterial, then etching the filler material part way into theindentation.
 4. A method according to claim 1, wherein the fillermaterial is polysilicon.
 5. A method according to claim 1, wherein alayer of dielectric is formed upon surfaces of the indentation prior tothe indentation being partially filled.
 6. A method according to claim5, wherein one or both of the dopants are introduced into the walls ofthe indentation through the dielectric layer.
 7. A method according toclaim 5, wherein the dielectric layer is at least partially removed fromthose surfaces of the indentation which are exposed above the partiallyfilled portion of the indentation, prior to the introduction of one orboth of the dopants.
 8. A method according to claim 1, wherein at leastone of the dopants is produced by an ionic source which is disposed atan angle to the indentation.
 9. A method according to claim 1, whereinat least a portion of a previously defined masking layer substantiallyprevents one or both of the dopants from entering at least a portion ofthe surface of the semiconductor body.
 10. A method according to claim9, wherein the thickness and composition of the previously definedmasking layer is such that it functions substantially as a barrier tothe introduction of one of the dopants but is substantially penetratedby the other dopant.
 11. A method according to claim 10, wherein the onedopant is introduced by ion implantation carried out at a relatively lowenergy and the other dopant is introduced by ion implantation carriedout at a relatively high energy.
 12. A method according to claim 1,wherein the first dopant is arranged to penetrate further into the sidewalls of the indentation than the second dopant.
 13. A method accordingto claim 1, wherein the second dopant is arranged to penetrate furtherinto the walls of the indentation than the first dopant.
 14. A methodaccording to claim 9, wherein at least a portion of the previouslydefined masking layer covering at least a portion of the surface of thesemiconductor body is arranged such that it functions substantially as abarrier to the introduction of the one dopant, but is at least partiallyremoved prior to introduction of the other dopant.
 15. A methodaccording to claim 1, wherein the first and second dopants are diffusedsimultaneously to form the first and second doped regions.
 16. A methodaccording to claim 1, wherein the semiconductor device is a MOSFET withgate regions provided by the filler material, body regions provided bythe deeper of the first and second doped regions, and source regionsprovided by the shallower of the first and second doped regions.
 17. Amethod according to claim 16, wherein the MOSFET is a n-channel (n-p-n)type structure.
 18. A method according to claim 16, wherein the MOSFETis a p-channel (p-n-p) type structure.
 19. A method according to claim1, wherein the semiconductor body is formed on a further body ofsemiconductor which defines a drain region.
 20. A method according toclaim 19, wherein a further layer of opposite conductivity type to thefurther body of semiconductor is formed on a side of the further body ofsemiconductor remote from the surface of the semiconductor body.